sihu国产精品永久免费_日韩午夜在线视频_久久99中文字幕伊人_古代男男嗯…啊h总攻

moecmks
級別: 正式會員
精華主題: 0
發(fā)帖數(shù)量: 3 個(gè)
工控威望: 96 點(diǎn)
下載積分: 648 分
在線時(shí)間: 24(小時(shí))
注冊時(shí)間: 2017-02-12
最后登錄: 2017-05-19
查看moecmks的 主題 / 回貼
樓主  發(fā)表于: 2017-04-24 19:39
先發(fā) FX1S數(shù)據(jù)讀報(bào)文,PLC接受到信號準(zhǔn)備數(shù)據(jù)放到緩沖區(qū)。然后在用ReadFile從緩沖區(qū)接受一次報(bào)文。。。 30 MS左右
這時(shí)間正常嗎?還是說我設(shè)置有問題?總感覺這樣時(shí)間有點(diǎn)長啊。【工控菜鳥一個(gè),放下代碼求老鳥指點(diǎn)一二,有無能提升效率的地方。 ^_^】

復(fù)制代碼
  1. #include <Windows.h>
  2. #include "codecb.h"
  3. #include "invariant.h"
  4. #include <assert.h>
  5. #include <tchar.h>
  6. #include "timing.h"
  7. extern HANDLE commport;
  8. _CRT_ALIGN (32)
  9. char ASCII_tonums_RVlut[0xFFFF+1];
  10. void build_ASC_RVlut (void)
  11. {
  12.   uint32_t ii;
  13.   static BOOL __init = FALSE;
  14.   if ( __init == TRUE) return;
  15.        __init  = TRUE;
  16.   ZeroMemory (ASCII_tonums_RVlut, sizeof (ASCII_tonums_RVlut));
  17.   for (ii = 0; ii != 0x10000; ii++) {
  18.    uint16_t lo = ii & 0x00FF;
  19.    uint16_t hi = ii >> 8;
  20.    if ( (( lo >= '0' && lo <= '9') || ( lo >= 'A' && lo <= 'F'))
  21.     && (( hi >= '0' && hi <= '9') || ( hi >= 'A' && hi <= 'F')))
  22.    {
  23.     if ( ( hi >= '0' && hi <= '9'))
  24.       ASCII_tonums_RVlut[ii] = hi - '0';
  25.     else if ( ( hi >= 'A' && hi <= 'F'))
  26.       ASCII_tonums_RVlut[ii] = hi - 'A' + 10;
  27.     if ( ( lo >= '0' && lo <= '9'))
  28.       ASCII_tonums_RVlut[ii] |= ( ( (unsigned) (lo - '0')) << 4);
  29.     else if ( ( lo >= 'A' && lo <= 'F'))
  30.       ASCII_tonums_RVlut[ii] |= ( ( (unsigned) (lo - 'A' + 10)) << 4);
  31.    }
  32.   }
  33. }
  34. BOOL comm_init (int comm_index)
  35. {
  36.   DCB dcbs;
  37.   COMMTIMEOUTS ct;  
  38.   BOOL success_io_;
  39.   TCHAR comm_buf0[256];
  40.   _stprintf (& comm_buf0[0], _T ("//./COM%i"), comm_index);
  41.   comm_close ();
  42.   commport = CreateFile ( & comm_buf0[0], GENERIC_READ | GENERIC_WRITE, 0,
  43.               NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL );
  44.   success_io_ = GetCommState (commport, & dcbs);
  45.   assert (success_io_ != FALSE);
  46.   dcbs.BaudRate = CBR_9600;
  47.   dcbs.fParity  = TRUE;
  48.   dcbs.Parity   = EVENPARITY;
  49.   dcbs.StopBits = ONESTOPBIT;
  50.   dcbs.ByteSize = 7;
  51.   dcbs.fDtrControl = DTR_CONTROL_DISABLE;
  52.   dcbs.fRtsControl = RTS_CONTROL_DISABLE;
  53.     
  54.   success_io_ = SetupComm (commport, 2048, 2048);
  55.   assert (success_io_ != FALSE);
  56.   success_io_ = SetCommState (commport, & dcbs);
  57.   assert (success_io_ != FALSE);
  58.   // SetTimeOut.
  59.   ct.ReadIntervalTimeout = 0x0000FFFF;
  60.   ct.ReadTotalTimeoutMultiplier = 0x0000FFFF;
  61.   ct.ReadTotalTimeoutConstant = 0xFFFFFFFE;
  62.   ct.WriteTotalTimeoutMultiplier = 0x0000FFFF;
  63.   ct.WriteTotalTimeoutConstant =   0xFFFFFFFE;  
  64.   
  65.   success_io_ = SetCommTimeouts (commport, &ct);  
  66.   assert (success_io_ != FALSE);
  67.   success_io_ = SetupComm (commport, 2400, 2400);  
  68.   assert (success_io_ != FALSE);
  69.   success_io_ = PurgeComm (commport, PURGE_RXABORT | PURGE_TXCLEAR | PURGE_RXCLEAR | PURGE_TXABORT);
  70.   assert (success_io_ != FALSE);
  71.   build_ASC_RVlut ();
  72.   
  73.   timing_init48 ();
  74.   INIT_WSCCRSEC__;
  75. }
  76. void comm_close (void)
  77. {
  78.   if (commport != INVALID_HANDLE_VALUE)
  79.   {
  80.     PurgeComm (commport, PURGE_RXABORT | PURGE_TXCLEAR | PURGE_RXCLEAR | PURGE_TXABORT);
  81.     CloseHandle (commport);
  82.   }
  83.   commport = INVALID_HANDLE_VALUE;
  84. }
  85. int8_t readOYB (int16_t e_addr) {
  86.   struct read_section2 rdsec;
  87.   char varsbuf[128];
  88.   int isr = 0;
  89.   int tm_numbs = 0;
  90.   uint16_t rv_numbs = 0;
  91.   BOOL io_success_;
  92.   DWORD rv_numbs2 = 0;
  93.   /* prepare Output-register read_section. */
  94.   isr = fx1s_makersecb ( & rdsec, FX1S_REGISTER_FIELD_Y_OUT,
  95.         & rv_numbs, FX1S_VERSION_30MR, e_addr);
  96.   assert (isr == FX1S_OK);
  97.   /* write Output-register read-code. */
  98.   io_success_ = WriteFile (commport, & rdsec,
  99.      sizeof(struct read_section), & tm_numbs, NULL);
  100.   assert (io_success_ != FALSE);
  101.   assert (tm_numbs == sizeof(struct read_section));
  102.   io_success_ = ReadFile  (commport, & varsbuf[0], rv_numbs, & rv_numbs2, NULL);
  103.   assert (io_success_ != FALSE);
  104.   assert (rv_numbs2 == rv_numbs);
  105.   assert (varsbuf[0] == SECTION_LINK_STX);
  106.   return ASCII_tonums_RVlut[ *(uint16_t *)& varsbuf[1]];
  107. }
  108. void setOYB (int16_t e_addr, int8_t val) {
  109.   char varsbuf[128];
  110.   int isr = 0;
  111.   int tm_numbs = 0;
  112.   uint16_t rv_numbs = 0;
  113.   BOOL io_success_;
  114.   DWORD rv_numbs2 = 0;
  115.   /* prepare Output-register write_section. */
  116.   isr = fx1s_makewsecb (& varsbuf[0], & val, FX1S_REGISTER_FIELD_Y_OUT,
  117.               & rv_numbs, FX1S_VERSION_30MR, e_addr);
  118.   assert (isr == FX1S_OK);
  119.   /* write Output-register write-code. */
  120.   io_success_ = WriteFile (commport, & varsbuf[0],
  121.      rv_numbs, & tm_numbs, NULL);
  122.   assert (io_success_ != FALSE);
  123.   assert (rv_numbs == tm_numbs);
  124.   io_success_ = ReadFile  (commport, & varsbuf[0], 1, & rv_numbs2, NULL);
  125.   assert (io_success_ != FALSE);
  126.   assert (rv_numbs2 == 1);
  127.   assert (varsbuf[0] == SECTION_LINK_ACK);
  128. }
  129. static __forceinline
  130. int8_t readRELAY_M (int16_t addr) {
  131.   struct read_section2 rdsec;
  132.   char varsbuf[128];
  133.   int isr = 0;
  134.   int tm_numbs = 0;
  135.   uint16_t rv_numbs = 0;
  136.   BOOL io_success_;
  137.   DWORD rv_numbs2;
  138.   isr = fx1s_makersecb ( & rdsec, FX1S_REGISTER_FIELD_M,
  139.         & rv_numbs, FX1S_VERSION_14MR, addr);
  140.   assert (isr == FX1S_OK);
  141.   io_success_ = WriteFile (commport, & rdsec,
  142.      sizeof(struct read_section), & tm_numbs, NULL);
  143.   assert (io_success_ != FALSE);
  144.   assert (tm_numbs == sizeof(struct read_section));
  145.   io_success_ = ReadFile  (commport, & varsbuf[0], rv_numbs, & rv_numbs2, NULL);
  146.   assert (io_success_ != FALSE);
  147.   assert (rv_numbs2 == rv_numbs);
  148.   assert (varsbuf[0] == SECTION_LINK_STX);
  149.   return ASCII_tonums_RVlut[ *(uint16_t *)& varsbuf[1]];
  150. }
  151. static  __forceinline
  152. void writeRELAY_M (uint16_t addr, int8_t val) {
  153.   char varsbuf[128];
  154.   int isr = 0;
  155.   int tm_numbs = 0;
  156.   uint16_t rv_numbs = 0;
  157.   BOOL io_success_;
  158.   DWORD rv_numbs2;
  159.   /* prepare Output-register write_section. */
  160.   isr = fx1s_makewsecb (& varsbuf[0], & val, FX1S_REGISTER_FIELD_M,
  161.               & rv_numbs, FX1S_VERSION_14MR, addr);
  162.   assert (isr == FX1S_OK);
  163.   /* write Output-register write-code. */
  164.   io_success_ = WriteFile (commport, & varsbuf[0],
  165.      rv_numbs, & tm_numbs, NULL);
  166.   assert (io_success_ != FALSE);
  167.   assert (rv_numbs == tm_numbs);
  168.   io_success_ = ReadFile  (commport, & varsbuf[0], 1, & rv_numbs2, NULL);
  169.   assert (io_success_ != FALSE);
  170.   assert (rv_numbs2 == 1);
  171.   assert (varsbuf[0] == SECTION_LINK_ACK);
  172. }
  173. void plc_force_close_ (void) {
  174.   BYTE obt;
  175.     /* force close PLC [by M8037]  **/
  176.     obt = readRELAY_M (8037);
  177.     writeRELAY_M (8037, obt | 0x20);
  178. }
  179. void plc_force_open_ (void) {
  180.   BYTE obt;
  181.   /* force open PLC [by M8035/M8036/M8037]  **/
  182.   obt = readRELAY_M (8037);
  183.   obt &= ~(1 << (8037 & 7));
  184.   writeRELAY_M (8037, obt);
  185.   obt = readRELAY_M (8035);
  186.   obt |= (11 << (8035 & 7));
  187.   writeRELAY_M (8035, obt);
  188. }
  189. void plc_set_pulse235_ (uint32_t val) {
  190.   int isr = 0;
  191.   char varsbuf[128];
  192.   uint16_t rv_numbs = 0;
  193.   DWORD rv_numbs2 = 0;
  194.   DWORD rv_numbs3 = 0;
  195.   BOOL io_success_;
  196.   isr = fx1s_makewsecb (& varsbuf[0], & val, FX1S_REGISTER_FIELD_C32,
  197.               & rv_numbs, FX1S_VERSION_14MR, PULSE_ENCODER_ADDR);
  198.   assert (isr == FX1S_OK);
  199.   rv_numbs2 = rv_numbs;
  200.   io_success_ = WriteFile (commport, & varsbuf[0], rv_numbs, & rv_numbs3, NULL);
  201.   assert (io_success_ != FALSE);
  202.   assert (rv_numbs2 == rv_numbs3);
  203.   io_success_ = ReadFile  (commport, & varsbuf[0], 1, & rv_numbs2, NULL);
  204.   assert (io_success_ != FALSE);
  205.   assert (rv_numbs2 == 1);
  206.   assert (varsbuf[0] == SECTION_LINK_ACK);
  207. }
  208. uint32_t plc_get_pulse235_ (void) {
  209.   union {
  210.     char bgroup[4];
  211.     int32_t inter;
  212.   } cc_timing;
  213.   BOOL io_success_;
  214.   DWORD rv_numbs = 0;
  215.   BYTE varsbuf[128];
  216.   io_success_ = WriteFile (commport, & g_crs2_pulse235.rsc, sizeof (struct read_section), & rv_numbs, NULL);
  217.   assert (io_success_ != FALSE);
  218.   assert (rv_numbs == sizeof (struct read_section));
  219.   io_success_ = ReadFile  (commport, & varsbuf [0], g_crs2_pulse235.rsc_cnt, & rv_numbs, NULL);
  220.   assert (io_success_ != FALSE);
  221.   assert (rv_numbs == g_crs2_pulse235.rsc_cnt);
  222.   assert (varsbuf[0] == SECTION_LINK_STX);
  223.   assert (varsbuf[9] == SECTION_LINK_ETX);
  224.   cc_timing.bgroup[0] = ASCII_tonums_RVlut[ *(uint16_t *)& varsbuf[1]];
  225.   cc_timing.bgroup[1] = ASCII_tonums_RVlut[ *(uint16_t *)& varsbuf[3]];
  226.   cc_timing.bgroup[2] = ASCII_tonums_RVlut[ *(uint16_t *)& varsbuf[5]];
  227.   cc_timing.bgroup[3] = ASCII_tonums_RVlut[ *(uint16_t *)& varsbuf[7]];
  228.   return cc_timing.inter;
  229. }


moecmks
級別: 正式會員
精華主題: 0
發(fā)帖數(shù)量: 3 個(gè)
工控威望: 96 點(diǎn)
下載積分: 648 分
在線時(shí)間: 24(小時(shí))
注冊時(shí)間: 2017-02-12
最后登錄: 2017-05-19
查看moecmks的 主題 / 回貼
1樓  發(fā)表于: 2017-04-24 19:48
FX1S 報(bào)文編解碼
復(fù)制代碼
  1. /*-
  2. * Copyright (c) 2017 moecmks
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions
  7. * are met:
  8. * 1. Redistributions of source code must retain the above copyright
  9. *    notice, this list of conditions and the following disclaimer.
  10. * 2. Redistributions in binary form must reproduce the above copyright
  11. *    notice, this list of conditions and the following disclaimer in the
  12. *    documentation and/or other materials provided with the distribution.
  13. *
  14. * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17. * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRCMD, STRICT
  22. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23. * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24. * SUCH DAMAGE.
  25. *
  26. */
  27. #if !defined (codec_included_MOECMKS)
  28. #define codec_included_MOECMKS
  29. /*
  30. * fx1s read/write codec.
  31. * simple, each read a current register size unit memory
  32. * more information, please refer to the PLC manual and Internet resources.
  33. */
  34. #if defined (__cplusplus)  /** __cplusplus */
  35. extern "C" {
  36. #endif  /** __cplusplus */
  37. /* Portable fixed length ***/
  38. #include "stdint.h"
  39. /*
  40. * errror code
  41. */
  42. #define FX1S_RANGE 1
  43. #define FX1S_FAIL 2
  44. #define FX1S_KFAIL 3
  45. #define FX1S_UNKN 4
  46. #define FX1S_LIMIT 5
  47. #define FX1S_NAK 6
  48. #define FX1S_ACK 7
  49. #define FX1S_PARA 8
  50. #define FX1S_INCOP 9
  51. #define FX1S_OK 0
  52. /*
  53. * version control
  54. */
  55. enum FX1S_VERSION {
  56.   FX1S_VERSION_10MR = 0,
  57.   FX1S_VERSION_14MR,
  58.   FX1S_VERSION_20MR,
  59.   FX1S_VERSION_30MR,
  60.   FX1S_VERSION_OVERFLAGS
  61. };
  62. /*
  63. * register field.
  64. * Ignore T bit register and set register.
  65. * Ignore C bit register
  66. */
  67. enum FX1S_REGISTER_FIELD {
  68.   FX1S_REGISTER_FIELD_S = 0,
  69.   FX1S_REGISTER_FIELD_X,
  70.   FX1S_REGISTER_FIELD_Y_OUT,
  71.   FX1S_REGISTER_FIELD_Y_PLS,
  72.   FX1S_REGISTER_FIELD_D,
  73.   FX1S_REGISTER_FIELD_T,
  74.   FX1S_REGISTER_FIELD_M,
  75.   FX1S_REGISTER_FIELD_C16,
  76.   FX1S_REGISTER_FIELD_C32,
  77.   FX1S_REGISTER_FIELD_CRESET
  78. };
  79. /*
  80. * section .link code
  81. */
  82. #define SECTION_LINK_STX 0x02 /* PLC info-section begin flags. */
  83. #define SECTION_LINK_ETX 0x03 /* PLC info-section end flags .***/
  84. #define SECTION_LINK_EOT 0x03 /* .***/
  85. #define SECTION_LINK_ENQ 0x05 /* PLC only test enable */
  86. #define SECTION_LINK_ACK 0x06 /* PLC reply "can do" */
  87. #define SECTION_LINK_LF 0x0A /* .***/
  88. #define SECTION_LINK_CL 0x0C /* .***/
  89. #define SECTION_LINK_CR 0x0D /* .***/
  90. #define SECTION_LINK_NAK 0x15 /* PLC reply "bad things" */
  91. /*
  92. * section cmdion.
  93. */
  94. #define SECTION_CMD_READ      '0' /* .***/
  95. #define SECTION_CMD_WRITE     '1' /* .***/
  96. #define SECTION_CMD_FORCE_ON  '7' /* .***/
  97. #define SECTION_CMD_FORCE_OFF '8' /* .***/
  98. /*
  99. * read section
  100. */
  101. struct read_section {
  102.   uint8_t stx; /* read_section's stdhead. always SECTIOM_LINK_STX */
  103.   uint8_t cmd; /* read_section's cmd  always SECTIOM_CMD_READ  */
  104.   uint8_t unit_address[4];  /* read_section's address*/
  105.   uint8_t numb[2];          /* read's byte count. simple always one */
  106.   uint8_t etx;    /* read_section's stdend.   always SECTION_LINK_ETX  */
  107.   uint8_t crc[2]; /* correcting code*/
  108. };
  109. /*
  110. * read section2
  111. */
  112. struct read_section2 {
  113.   uint8_t stx; /* read_section's stdhead. always SECTIOM_LINK_STX */
  114.   uint8_t cmd; /* read_section's cmd  always SECTIOM_CMD_READ  */
  115.   uint8_t unit_address[4];  /* read_section's address*/
  116.   uint8_t numb[2];          /* read's byte count. simple always one */
  117.   uint8_t etx;    /* read_section's stdend.   always SECTION_LINK_ETX  */
  118.   uint8_t crc[2]; /* correcting code*/
  119.   uint8_t crce; /* easy to read..**/
  120.   uint16_t opbsize; /******/
  121.   uint8_t opboff; /* for bit register(X, Y, M.) **/
  122.   uint16_t opbaddr; /* easy to read. **/
  123. };
  124. /*
  125. * write section
  126. */
  127. struct write_section {
  128.   uint8_t stx; /* write_section's stdhead.  always SECTIOM_LINK_STX */
  129.   uint8_t cmd; /* write_section's cmd  always SECTIOM_CMD_WRITE   */
  130.   uint8_t unit_address[4]; /* write_section's address*/
  131.   uint8_t numb[2]; /* write's byte count.. must <= 64  */
  132.   uint8_t etx; /* write_section's stdend. */
  133.   uint8_t crc[2]; /* correcting code*/
  134.   uint8_t crce; /* easy to read..**/
  135.   uint8_t obpoff; /* for bit register(X, Y, M.) **/
  136.   uint16_t opbaddr; /* easy to read. **/
  137. };
  138. /*
  139. * force section
  140. */
  141. struct force_section {
  142.   uint8_t stx; /* force_section's stdhead.  always SECTIOM_LINK_STX */
  143.   uint8_t cmd; /* force_section's cmd  always SECTIOM_CMD_FORCE_OFF or SECTIOM_CMD_FORCE_ON   */
  144.   uint8_t unit_address[4]; /* force_section's address*/
  145.   uint8_t etx; /* force_section's stdend. */
  146.   uint8_t crc[2]; /* correcting code*/
  147. };
  148. /*
  149. * Accept the write section is very simple,
  150. * if successful send SECTION_LINK_ACK otherwise SECTION_LINK_NAK
  151. */
  152. int fx1s_makersecb (struct read_section2 *rsec, /* write to the serial port, use the size of the read_section */
  153.                          enum FX1S_REGISTER_FIELD rf, uint16_t  *rvap_size,
  154.                          enum FX1S_VERSION ver, uint16_t address);
  155. int fx1s_makewsecb (void *wsec, /* Variable size structure, so use void *, please understand **/
  156.                    void *spval,
  157.                          enum FX1S_REGISTER_FIELD rf, uint16_t  *wsec_size,
  158.                          enum FX1S_VERSION ver, uint16_t address);
  159. int fx1s_makefsecb (struct force_section *fsec,
  160.                          enum FX1S_REGISTER_FIELD rf,
  161.                          enum FX1S_VERSION ver, uint16_t address);            
  162. #if defined (__cplusplus)  /** __cplusplus */
  163. }
  164. #endif  /** __cplusplus */
  165. #endif /* codec_included_MOECMKS */
moecmks
級別: 正式會員
精華主題: 0
發(fā)帖數(shù)量: 3 個(gè)
工控威望: 96 點(diǎn)
下載積分: 648 分
在線時(shí)間: 24(小時(shí))
注冊時(shí)間: 2017-02-12
最后登錄: 2017-05-19
查看moecmks的 主題 / 回貼
2樓  發(fā)表于: 2017-04-24 19:52
復(fù)制代碼
  1. /*-
  2. * Copyright (c) 2017 moecmks
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions
  7. * are met:
  8. * 1. Redistributions of source code must retain the above copyright
  9. *    notice, this list of conditions and the following disclaimer.
  10. * 2. Redistributions in binary form must reproduce the above copyright
  11. *    notice, this list of conditions and the following disclaimer in the
  12. *    documentation and/or other materials provided with the distribution.
  13. *
  14. * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17. * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23. * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24. * SUCH DAMAGE.
  25. *
  26. */
  27. #include <assert.h>
  28. #include <string.h>
  29. #include "codecb.h"
  30. /* Convert characters to specific number - noexport */
  31. static
  32. char ascii_to_num (char ch) {
  33.   /* e.g.
  34.    *  source '9' -> target 9
  35.    *  source 'A' -> target 10
  36.    *  source '1' -> target 1
  37.    *  source 'a' -> (nondone, Don't use lowercase letters in fx1s-14mr-001).
  38.    */
  39.   if (ch >= '0' && ch <= '9')
  40.     return (ch - '0');
  41.   if (ch >= 'A' && ch <= 'F')
  42.     return (ch - ('A' - 10));
  43.   else
  44.     assert (0);
  45.   return ch;
  46. }
  47. /* Convert number to specific characters - noexport */
  48. static
  49. char num_to_ascii (char ch) {
  50.   /* e.g.
  51.    *  source 9 -> target '9'
  52.    *  source A -> target '0'
  53.    *  source 1 -> target '1'
  54.    *  source a -> (nondone, Don't use lowercase letters in fx1s-14mr-001).
  55.    */
  56.   if (ch >= 0x00 && ch <= 0x09)
  57.     return (ch + '0');
  58.   if (ch >= 0x0A && ch <= 0x0F)
  59.     return (ch + ('A' - 10));
  60.   else
  61.     assert (0);
  62.   return ch;
  63. }
  64. /* XXX:L-endian.
  65. */
  66. static
  67. uint16_t vailed8 (uint16_t nums) {
  68.   
  69.   /* e.g.
  70.    * 1234 vailed.
  71.    * 9000 invailed.
  72.    * 1007 vailed.
  73.    * 1811 invailed.
  74.    * 0 ~ 65535
  75.    */
  76.    uint16_t d0 = nums % 10 >> 0;
  77.    uint16_t d1 = nums % 100 / 10;
  78.    uint16_t d2 = nums % 1000 / 100;
  79.    uint16_t d3 = nums % 10000 / 1000;
  80.   
  81.    if ( d0 > 7 || d1 > 7)
  82.      return -1;
  83.    if ( d2 > 7)
  84.      return -1;
  85.    return d0 + d1 * 8 + d2 * 8 * 8 + d3 * 8 * 8 * 8;
  86. }
  87. static
  88. uint8_t fxcrc_adjust (unsigned char *crcbuf, uint32_t num) {
  89.   
  90.   uint32_t s= 0;
  91.   uint32_t st = 0;
  92.   
  93.   for (; s != num; s++)
  94.     st += crcbuf[s];
  95.   /* we only save lowest bit's byte **/
  96.   return st & 0xFF;
  97. }
  98. static /* we not check numb cross register **.**/
  99. uint32_t fxcalc_addru (enum FXREGS_FIELD reg, uint16_t addr,
  100.                            enum FX1S_VERSION ver,
  101.                            uint16_t  *opbsize,
  102.                                 uint16_t *raddr, unsigned char *dboff) {
  103.   
  104.   static const /* XXX:enum constant dependence **/
  105.                    uint16_t xmax_tab[4] = { 6, 8, 12, 16 };
  106.   static const /* XXX:enum constant dependence **/
  107.                    uint16_t ymax_tab[4] = { 4, 6, 8, 14 };
  108.   uint16_t addr0 = 0x00A0;
  109.   uint16_t eig = vailed8 (addr);
  110.   uint8_t off = -1;
  111.   uint32_t opbsize0 = 2;
  112.   switch (reg) {
  113.     
  114.   case FX1S_REGISTER_FIELD_D:
  115.   
  116.     if (addr <= 127 && addr == addr) /* numbers: 128, normal use */
  117.       addr0 = 0x1000 + addr * 2;
  118.     else if (addr <= 255) /* numbers: 128, save use */
  119.       addr0 = 0x1000 + addr * 2;
  120.     else if (addr >= 1000 && addr <= 2499)  /* numbers: 1500, file register */
  121.       addr0 = 0x1000 + addr * 2;
  122.     else if (addr >= 8000 && addr <= 8255) /* numbers: 256, special IO port */
  123.       addr0 = 0x0E00 + (addr - 8000) * 2;
  124.     else  /* Illegal access */
  125.       return FX1S_RANGE;
  126.     break;
  127.   case FX1S_REGISTER_FIELD_X:
  128.     /*
  129.      * Check the number of available X-coils according to the PLC version
  130.      */
  131.     if ((eig = vailed8 (addr)) == -1
  132.      || (eig >= xmax_tab[ver]) )
  133.       return FX1S_PARA;
  134.       
  135.     addr0 = 0x0080 + eig / 8;
  136.     off = eig & 7;
  137.     
  138.     opbsize0 = 1;
  139.     break;
  140.     
  141.   case FX1S_REGISTER_FIELD_Y_PLS:
  142.     addr0 += 0x0200;
  143.   case FX1S_REGISTER_FIELD_Y_OUT:
  144.   
  145.     /*
  146.      * Check the number of available Y-coils according to the PLC version
  147.      */
  148.     if ((eig = vailed8 (addr)) == -1)
  149.       return FX1S_PARA;
  150.     
  151.     addr0 += eig / 8;
  152.     off = eig & 7;
  153.     
  154.     opbsize0 = 1;
  155.     break;
  156.   case FX1S_REGISTER_FIELD_S:
  157.   
  158.     if ((addr >=  128)) /* numbers:128, status register **/
  159.       return FX1S_RANGE;
  160.     addr0 = addr / 8;
  161.     off = addr & 7;
  162.     
  163.     opbsize0 = 1;
  164.     break;
  165.   
  166.   case FX1S_REGISTER_FIELD_T:
  167.   
  168.     if ( (addr <=  63)) /* numbers:64, 100ms or 10ms M8028/D8030/D8031 **/
  169.       addr0 = 0x0800 + addr * 2;
  170.     else    
  171.       return FX1S_RANGE;
  172.     break;
  173.     
  174.   case FX1S_REGISTER_FIELD_M:
  175.   
  176.     if (addr < 384) /* numbers: 384, normal use */
  177.       addr0 = 0x0100 + addr / 8;
  178.     else if (addr < 512) /* numbers: 512, save use */
  179.       addr0 = 0x0100 + addr / 8;
  180.     else if (addr >= 8000 && addr < 8256) /* numbers: 256, special IO port */
  181.       addr0 = 0x01E0 + (addr - 8000) / 8;
  182.     else /* Illegal access */
  183.       return FX1S_RANGE;
  184.     
  185.     off = addr & 7;
  186.     opbsize0 = 1;
  187.     break;
  188.   
  189.   case FX1S_REGISTER_FIELD_C16:
  190.   
  191.     if (addr < 16) /* numbers: 16, normal use */
  192.       addr0 = 0x0A00 + addr * 2;
  193.     else if (addr < 32) /* numbers: 16, save use */
  194.       addr0 = 0x0A00 + addr * 2;
  195.     else /* Illegal access */
  196.       return FX1S_RANGE;
  197.     break;
  198.     
  199.   case FX1S_REGISTER_FIELD_C32:
  200.   
  201.    /* for C32 high speed registers,
  202.     * we only perform some basic checks, please note
  203.     **/
  204.     if (addr > 200 && addr <= 255)
  205.       addr0 = 0x0C00 + (addr - 200) * 4;
  206.     else /* Illegal access */
  207.       return FX1S_RANGE;
  208.       
  209.     opbsize0 = 4;
  210.     break;
  211.   
  212.   case FX1S_REGISTER_FIELD_CRESET:
  213.   
  214.     if (addr <= 255)
  215.       addr0 = 0x03C0 + addr / 8;
  216.     else /* Illegal access */
  217.       return FX1S_RANGE;
  218.       
  219.     opbsize0 = 1;
  220.     break;
  221.     
  222.   default:
  223.       return FX1S_PARA;
  224.   }
  225.   
  226.   *raddr = addr0;
  227.   *dboff = off;
  228.   *opbsize = opbsize0;
  229.   return FX1S_OK;
  230. }
  231. int fx1s_makersecb (struct read_section2 *rsec, /* write to the serial port, use the size of the read_section */
  232.                          enum FX1S_REGISTER_FIELD rf, uint16_t  *rvap_size,
  233.                          enum FX1S_VERSION ver, uint16_t address)
  234. {
  235.   struct read_section2 sec;
  236.   uint32_t e;
  237.   
  238.   /** phase 1:fill stdhead/stdend flags and cmd, rread count,s */
  239.   sec.stx = SECTION_LINK_STX;
  240.   sec.etx = SECTION_LINK_ETX;
  241.   sec.cmd = SECTION_CMD_READ;
  242.   /** phase 2:calc address for register and current PLC version */
  243.   e = fxcalc_addru (rf, address, ver, & sec.opbsize, & sec.opbaddr, & sec.opboff);
  244.   if (e != FX1S_OK)
  245.     return e;
  246.   else
  247.    *rvap_size = sizeof (sec.stx) +
  248.                 sizeof (sec.crc)+ sizeof (sec.etx) + sec.opbsize * 2;
  249.   /** phase 3:fill numb ascii, * */
  250.   sec.numb[0] = num_to_ascii ( (sec.opbsize  & 0xF0) >>4);
  251.   sec.numb[1] = num_to_ascii ( (sec.opbsize  & 0x0F) >>0);
  252.   
  253.   /** phase 4:fill address ascii, * */
  254.   sec.unit_address[0] = num_to_ascii ( (sec.opbaddr  & 0xF000) >>12);
  255.   sec.unit_address[1] = num_to_ascii ( (sec.opbaddr  & 0x0F00) >> 8);
  256.   sec.unit_address[2] = num_to_ascii ( (sec.opbaddr  & 0x00F0) >> 4);
  257.   sec.unit_address[3] = num_to_ascii ( (sec.opbaddr  & 0x000F) >> 0);
  258.   
  259.   /** phase 5:crc adjust, fill ascii buf * */
  260.   sec.crce = fxcrc_adjust (& sec.cmd, sizeof (sec.cmd) + sizeof (sec.unit_address)
  261.                                         + sizeof (sec.numb)
  262.                                         + sizeof (sec.etx));
  263.   sec.crc[0] = num_to_ascii ( (sec.crce  & 0xF0) >> 4);
  264.   sec.crc[1] = num_to_ascii ( (sec.crce  & 0x0F) >> 0);
  265.   
  266.   memcpy (rsec, & sec, sizeof (sec));
  267.   return FX1S_OK;  
  268. }
  269. int fx1s_makewsecb (void *wsec, /* Variable size structure, so use void *, please understand **/
  270.                    void *buf, /* wsec size == sizeof(wc) * 2  **/
  271.                          enum FX1S_REGISTER_FIELD rf, uint16_t *wsec_size,
  272.                          enum FX1S_VERSION ver, uint16_t address)
  273. {
  274.   uint16_t opbsize, opbaddr;
  275.   char obpoff;
  276.   char varsbuf[256];
  277.   char *as = buf, cs;
  278.   uint32_t e;
  279.   uint32_t s = 0;
  280.   struct write_section *secp = wsec;
  281.   struct write_section *secdp = (void *)varsbuf;
  282.   /** phase 1:fill stdhead flags and cmd */
  283.   secdp->stx = SECTION_LINK_STX;
  284.   secdp->cmd = SECTION_CMD_WRITE;
  285.   /** phase 2:calc address for register and current PLC version */
  286.   e = fxcalc_addru (rf, address, ver, & opbsize, & opbaddr, & obpoff);
  287.   if (e != FX1S_OK)
  288.     return e;
  289.   else
  290.     *wsec_size = sizeof (struct write_section) + opbsize * 2;
  291.   /** phase 3:fill numb ascii, * */
  292.   secdp->numb[0] = num_to_ascii ( (opbsize  & 0xF0) >>4);
  293.   secdp->numb[1] = num_to_ascii ( (opbsize  & 0x0F) >>0);
  294.   
  295.   /** phase 4:fill address ascii, * */
  296.   secdp->unit_address[0] = num_to_ascii ( (opbaddr  & 0xF000) >>12);
  297.   secdp->unit_address[1] = num_to_ascii ( (opbaddr  & 0x0F00) >> 8);
  298.   secdp->unit_address[2] = num_to_ascii ( (opbaddr  & 0x00F0) >> 4);
  299.   secdp->unit_address[3] = num_to_ascii ( (opbaddr  & 0x000F) >> 0);
  300.   
  301.   /** phase 5:fill variable buffer, * */
  302.   for ( ; s != opbsize; s++) {
  303.     unsigned char  temp = as[s];
  304.     char  tmphi = num_to_ascii (temp >> 4);
  305.     char  tmplo = num_to_ascii (temp & 15);
  306.     
  307.     secdp->numb[2+s*2+0] = tmphi;
  308.     secdp->numb[2+s*2+1] = tmplo;
  309.   }
  310.   /** phase 6:crc adjust, fill ascii buf * */
  311.   secdp->numb[2+opbsize*2] = SECTION_LINK_ETX;
  312.   
  313.   cs = fxcrc_adjust (& secdp->cmd, opbsize * 2 + sizeof (secp->cmd) + sizeof (secp->unit_address)
  314.                                         + sizeof (secp->numb)
  315.                                         + sizeof (secp->etx));
  316.   secdp->numb[2+opbsize*2+1] = num_to_ascii ( (cs  & 0xF0) >> 4);
  317.   secdp->numb[2+opbsize*2+2] = num_to_ascii ( (cs  & 0x0F) >> 0);
  318.   
  319.   memcpy (wsec, & varsbuf, *wsec_size);
  320.   return FX1S_OK;
  321. }
  322. uint32_t fx1s_cmprvpack (void *raccbuf, /* Variable size structure, so use void *, please understand **/
  323.                          uint16_t rc, void **ascii_buf, uint16_t *opbsize
  324.                          , uint16_t *stdpos)
  325. {
  326.   char *varsbuf = raccbuf;
  327.   uint16_t c = 0;
  328.   char stx_find = 0;
  329.   uint16_t stdpos0 = -1;
  330.   
  331.   /* we find SECTION_LINK_NAK or SECTION_LINK_STX at first **/
  332.   for (; c != rc; c++)
  333.    {
  334.      if (varsbuf[c] == SECTION_LINK_NAK)
  335.        return FX1S_NAK;
  336.      if (varsbuf[c] == SECTION_LINK_STX)
  337.       {
  338.         /* second, we check SECTION_LINK_ETX in buffer **/
  339.         stx_find = 1;
  340.         stdpos0 = c + 1;
  341.       }  
  342.      if (varsbuf[c] == SECTION_LINK_ETX && stx_find == 1)
  343.       {
  344.         /* exist CRC byte ??**/
  345.         if ((c + 2) >= rc)
  346.           return FX1S_INCOP;
  347.         /* calculate, compare the CRC code **/
  348.         {
  349.       # if 0
  350.       # else
  351.           *ascii_buf = & varsbuf[stdpos0];
  352.           *opbsize = c - stdpos0;
  353.           *stdpos = stdpos0;
  354.           return FX1S_OK;
  355.       # endif    
  356.         }
  357.       }
  358.    }
  359.   
  360.    return FX1S_INCOP;
  361. }                    
  362. uint32_t fx1s_decrvsec (void *raccbuf, void *sbuf, uint16_t opbasize) {
  363.   
  364.   char *varsbuf = raccbuf;
  365.   char *ssbuf = sbuf;
  366.   uint16_t c = 0;
  367.   
  368.   if (opbasize % 2 == 1)
  369.     return FX1S_INCOP;
  370.   if (opbasize == 0)
  371.     return FX1S_PARA;
  372.   
  373.   for ( ; c != opbasize; c += 2)
  374.     {
  375.       char tmphi = ascii_to_num (varsbuf[c]) << 4;
  376.       char tmplo = ascii_to_num (varsbuf[c+1]);  
  377.       char temp  =   (tmphi & 0xF0) |    (tmplo & 0x0F);
  378.       
  379.       ssbuf[c>>1] = temp;
  380.     }
  381.     
  382.     return FX1S_OK;
  383. }